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general description the max15018a/max15018b/max15019a/max15019b high-frequency, 125v half-bridge, n-channel mosfet drivers drive high- and low-side mosfets in high-volt- age applications. these drivers are independently con- trolled, and their 35ns (typ) propagation delay, from input to output, are matched to within 2ns (typ). the high-volt- age operation with very low and matched propagation delay between drivers, and high source-/sink-current capabilities in a thermally enhanced package make these devices suitable for high-power, high-frequency telecom power converters. the 125v maximum input voltage provides plenty of margin over the 100v input transient requirement of telecom standards. a reliable on-chip bootstrap diode connected between v dd and bst eliminates the need for an external discrete diode. the max15018a/max15019a both offer noninverting dri- vers. the max15018b/max15019b offer a noninverting high-side driver and an inverting low-side driver (see the selector guide .) the max15018_ feature cmos (v dd /2) logic inputs. the max15019_ feature ttl-logic inputs. the drivers are available in the industry-standard 8-pin so footprint and pin configuration with a thermally enhanced 8-pin so package. all devices operate over the -40? to +125? automotive temperature range. applications telecom power supplies synchronous buck dc-to-dc converters half-bridge, full-bridge, and two-switch forward converters power-supply modules motor control features hip2100ib/hip2101ib pin compatible (max15018a/max15019a) up to 125v v in operation 8v to 12.6v v dd input supply range 3a peak source and sink current 35ns propagation delay guaranteed 8ns or less propagation delay matching between high- and low-side drivers both noninverting/noninverting and noninverting/inverting logic-input versions available up to 15v logic inputs, independent of v dd supply voltage low 8pf input capacitance available in cmos (v dd /2) or ttl logic-level inputs with hysteresis available in a space-saving, thermally enhanced 8-pin so-ep package max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers ________________________________________________________________ maxim integrated products 1 max15018a max15018b max15019a max15019b 8 1 v dd dl 7 2 bst gnd 6 3 dh in_l 5 4 hs in_h so-ep top view + pin configuration ordering information max15018a max15019a bst dh hs v dd dl pwm1 pwm2 in_h in_l v out v in = 0 to 125v n n c bst v dd = 8v to 12.6v c vdd gnd part temp range pin-package max15018 aasa+ -40? to +125? 8 so-ep* MAX15018BASA+ -40? to +125? 8 so-ep* max15019 aasa+ -40? to +125? 8 so-ep* max15019basa+ -40? to +125? 8 so-ep* typical operating circuit 19-4146; rev 1; 9/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead-free/rohs-compliant package. * ep = exposed pad. internally connected to gnd.
max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = v bst = 8v to 12.6v, v hs = v gnd = 0v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at v dd = v bst = 12v and t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ............................................................-0.3v to +15v in_h, in_l to gnd .................................................-0.3v to +15v dl to gnd ..................................................-0.3v to (v dd + 0.3v) dh to hs.....................................................-0.3v to (v dd + 0.3v) bst to hs ...............................................................-0.3v to +15v hs to gnd (repetitive transient)..............................-5v to +130v hs dv/dt to gnd................................................................50v/ns continuous power dissipation (t a = +70?) single and multilayer board 8-pin so-ep (derate 23.8mw/? above +70?)*..........1.904w jc ...................................................................................6?/w operating temperature .....................................-40? to +125? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units power supply operating supply voltage v vdd 8.0 12.6 v max15018a/ max15018b 65 130 v dd quiescent supply current i ddq in_h and in_l are unconnected (no switching) max15019a/ max15019b 95 190 ? v dd operating supply current i ddo f sw = 500khz, v dd = 12v, no capacitive load 2.75 3.75 ma bst quiescent supply current i bstq in_h and in_l are unconnected (no switching) 95 190 ? bst operating supply current i bsto f sw = 500khz, v bst - v hs = 12v, no capacitive load 2.75 3.75 ma uvlo (v dd to gnd) v dd_uvlo v dd rising 6.5 7.3 8 v uvlo (bst to hs) v bst_uvlo v bst rising 6.2 6.9 7.6 v uvlo hysteresis 0.5 v logic input max15018a/max15018b (cmos) 0.67 x v dd input-logic high v ih max15019a/max15019b (ttl) 2 v max15018a/max15018b (cmos) 0.33 x v dd input-logic low v il max15019a/max15019b (ttl) 0.8 v max15018a/max15018b (cmos) 1.65 logic-input hysteresis v hys max15019a/max15019b (ttl) 0.4 v * as per jedec standard 51 (single-layer board).
max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units in_h = in_l = gnd (max15018a/max15019a) logic-input current i in_ in_h = gnd, in_l = v dd (max15018b/max15019b) -1 +1 ? in_l to gnd (max15018a/max15019a) in_l to v dd (max15018b/max15019b) input resistance r in_ in_h to gnd 5001 k ? input capacitance c in_ 8pf high-side gate driver hs maximum voltage v hs_max 125 v bst maximum voltage v bst_max 140 v t a = +25? 1.75 2.4 r on_hp (v bst - v hs ) = 12v, i dh = 100ma (sourcing) t a = +125? 2.3 3.0 t a = +25? 1.1 1.75 driver output resistance r on_hn (v bst - v hs ) = 12v, i dh = 100ma (sinking) t a = +125? 1.6 2.25 ? power-off pulldown clamp voltage v bst = 0v or unconnected, i dh = 1ma (sinking) 0.88 1.2 v i pk_hp v dh = 0v 3 peak output current i pk_hn v dh = 12v 3 a low-side gate driver t a = +25? 1.75 2.4 r on_lp v dd = 12v, i dl = 100ma (sourcing) t a = +125? 2.3 3.0 t a = +25? 1.1 1.75 driver output resistance r on_ln v dd = 12v, i dl = 100ma (sinking) t a = +125? 1.6 2.25 ? power-off pulldown clamp voltage v dd = 0v or unconnected, i dl = 1ma (sinking) 0.88 1.2 v i pk_lp v dl = 0v 3 peak output current i pk_ln v dl = 12v 3 a internal bootstrap diode forward voltage drop v f i bst = 100ma 0.9 1.1 v turn-on and turn-off time t rr i bst = 100ma 40 ns electrical characteristics (continued) (v dd = v bst = 8v to 12.6v, v hs = v gnd = 0v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at v dd = v bst = 12v and t a = +25?.) (note 1)
max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = v bst = 8v to 12.6v, v hs = v gnd = 0v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at v dd = v bst = 12v and t a = +25?.) (note 1) parameter symbol conditions min typ max units switching characteristics for high- and low-side drivers (v dd = v bst = +12v) no c l 1 c l = 1000pf 5 c l = 5000pf 25 rise time t r c l = 10,000pf 50 ns no c l 1 c l = 1000pf 5 c l = 5000pf 20 fall time t f c l = 10,000pf 40 ns max15018a/ max15018b (cmos) 33 60 turn-on propagation delay time t d_on figure 1, c l = 1000pf (note 2) max15019a/ max15019b (ttl) 36 66 ns max15018a/ max15018b (cmos) 30 55 turn-off propagation delay time t d_off figure 1, c l = 1000pf (note 2) max15019a/ max15019b (ttl) 36 66 ns max15018a/ max15018b (cmos) 15 delay matching between high-side turn-on to low-side turn-on t match1 c l = 1000pf (note 2) max15019a/ max15019b (ttl) 16 ns max15018a/ max15018b (cmos) 15 delay matching between high-side turn-off to low-side turn-off t match2 c l = 1000pf (note 2) max15019a/ max15019b (ttl) 16 ns max15018a/ max15018b (cmos) 28 delay matching between high-side turn-off to low-side turn-on t match3 c l = 1000pf (note 2) max15019a/ max15019b (ttl) 16 ns max15018a/ max15018b (cmos) 28 delay matching between high-side turn-on to low-side turn-off t match4 c l = 1000pf (note 2) max15019a/ max15019b (ttl) 16 ns minimum input pulse width for output change t pw 20 ns note 1: all devices are 100% production tested at t a = t j = +125?. limits over temperature are guaranteed by design and char- acterization. note 2: guaranteed by design, not production tested.
max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 5 v dd and bst undervoltage lockout vs. temperature max15018 toc01 ambient temperature ( c) v uvlo (v) 110 95 65 80 -10 5 20 35 50 -25 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 6.5 -40 125 v dd rising v bst - v hs rising v dd and bst undervoltage lockout hysteresis vs. temperature max15018 toc02 ambient temperature ( c) hysteresis (v) 110 95 65 80 -10 5 20 35 50 -25 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 0.40 -40 125 v dd v bst - v hs undervoltage lockout response (v dd rising) max15018 toc03 40 s/div v dd 2v/div v dh 5v/div v dl 5v/div 4v 7.3v 12v undervoltage lockout response (v dd falling) max15018 toc04 40 s/div v dd 2v/div v dh 5v/div v dl 5v/div 4v 6.8v 12v max15018a i ddo + i bsto current vs. v dd (250khz switching) max15018 toc05 v dd (v) i dd + i bst (ma) 10 9 78 23456 1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0111213 v dd falling v dd rising v dd = v bst internal bootstrap diode i-v characteristics max15018 toc06 v dd - v bst (v) diode current (ma) 0.8 0.7 0.4 0.5 0.6 20 40 60 80 100 120 140 160 180 200 0 0.3 0.9 1.0 t a = -40 c t a = 0 c t a = +25 c t a = +125 c t a = +150 c max15018a v dd quiescent current vs. v dd (no switching) max15018 toc07 v dd (v) i dd ( a) 20 40 80 60 100 120 140 160 0 v dd falling t a = -40 c, 0 c, +25 c t a = +125 c t a = +150 c 11 10 9 78 23456 1 0121315 14 max15018a bst quiescent current vs. v bst (no switching) max15018 toc08 v bst (v) i bst ( a) 11 10 9 78 23456 1 20 40 60 80 100 120 140 0 0121315 14 v bst falling t a = -40 c t a = 0 c t a = +25 c t a = +125 c max15018a i dd and i bst vs. switching frequency max15018 toc09 switching frequency (khz) supply current (ma) 600 200 400 1 2 3 4 5 6 0 0 800 1000 v dd = v bst = 12v no load i bst i dd typical operating characteristics (t a = +25?, unless otherwise noted.)
max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers 6 _______________________________________________________________________________________ typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) dh or dl output low voltage vs. temperature max15018 toc10 ambient temperature ( c) output voltage (mv) 125 110 95 65 80 -10 5 20 35 50 -25 80 100 120 140 160 180 200 60 -40 sinking 100ma dh and dl output high voltage vs. temperature max15018 toc11 ambient temperature ( c) output voltage (mv) 125 110 95 65 80 -10 5 20 35 50 -25 120 160 140 180 200 220 240 260 280 300 100 -40 sourcing 100ma v dd - v dl v bst - v dh peak output current vs. output voltage max15018 toc12 v dh or v dh (v) i out (a) 12 11 10 9 78 23456 1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0 sink (nmos) source (pmos) dh or dl output rise time vs. temperature max15018 toc13 ambient temperature ( c) rise time (ns) 125 110 95 65 80 -10 5 20 35 50 -25 10 20 30 40 50 60 70 80 90 100 0 -40 10,000pf load dh or dl output fall time vs. temperature max15018 toc14 ambient temperature ( c) fall time (ns) 125 110 95 65 80 -10 5 20 35 50 -25 20 10 30 40 50 60 70 90 80 100 0 -40 10,000pf load dh or dl rising propagation delay vs. temperature max15018 toc15 ambient temperature ( c) propagation delay (ns) 125 110 95 65 80 -10 5 20 35 50 -25 10 20 30 40 50 60 0 -40 max15019 max15018 dh or dl falling propagation delay vs. temperature max15018 toc16 ambient temperature ( c) propagation delay (ns) 125 110 95 65 80 -10 5 20 35 50 -25 10 20 30 40 50 60 0 -40 max15019 max15018 delay matching (dh and dl rising) max15018 toc17 10ns/div v in_ 10v/div v dh and v dl 10v/div c l = 0pf
max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 7 delay matching (dh and dl rising) max15018 toc18 10ns/div v in_ 10v/div v dh and v dl 10v/div c l = 0pf response to v dd glitch max15018 toc19 40 s/div v dh_ v in_ v dl v dd 10v/div 10v/div 10v/div 10v/div typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) _______________________________________________________________________________________ 7 pin description pin name function 1v dd input supply voltage. valid supply voltage ranges from 8v to 12.6v. bypass v dd to gnd with a parallel combination of 0.1? and 1? ceramic capacitors as close to the ic as possible. 2 bst boost flying capacitor connection. connect a 0.22? ceramic capacitor from bst to hs as close to the ic as possible for the high-side mosfet driver supply. 3 dh high-side gate driver output. driver output for the high-side mosfet gate. 4 hs source connection for high-side mosfet. also serves as the return for the high-side driver. 5 in_h high-side noninverting logic input 6 in_l low-side noninverting (max15018a/max15019a) or low-side inverting (max15018b/max15019b) input 7 gnd ground. use gnd as a return path to the dl driver output and the in_h, in_l inputs. must be connected to ground. 8 dl low-side gate driver output. driver output for the low-side mosfet gate. ?p exposed pad. internally connected to gnd. externally connect the exposed pad to a large ground plane to aid in heat dissipation. grounding ep does not substitute the requirement to connect gnd to ground.
max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers 8 _______________________________________________________________________________________ detailed description the max15018a/max15018b/max15019a/max15019b half-bridge, n-channel mosfet drivers control high- and low-side mosfets in high-voltage, high peak-cur- rent applications and offer a high 125v voltage range that allows ample margin above the 100v transient specification of telecom standards. these drivers oper- ate with an ic supply voltage of 8v to 12.6v, and con- sume only 2.75ma of supply current during typical switching operations. the max15018_/max15019_ pro- vide 3a (typ) sink/source peak current per output and are capable of operating with large capacitive loads and with switching frequencies near 1mhz. these drivers are intended to be used to drive the high-side mosfet without requiring an isolation device such as an optocoupler or a drive transformer. the high-side driver is controlled by a ttl/cmos logic sig- nal referenced to ground and is powered by a boot- strap circuit formed by an integrated diode and an external capacitor. undervoltage lockout (uvlo) pro- tection is provided for both the high- and low-side dri- ver supplies (bst and v dd ) and includes a uvlo hysteresis of 0.5v (typ). the drivers are independently controlled and feature exceptionally fast switching times, very short propaga- tion delays (35ns typ), and matched propagation delay- times (2ns typ) between drivers, making them ideally suited for high-frequency applications. internal logic cir- cuitry prevents shoot-through during output state changes and minimizes package power dissipation. these devices are available with cmos (v dd /2) or ttl logic-level inputs. the max15018a/max15018b accept cmos input logic levels, while the max15019a/ max15019b accept ttl input logic levels. for both ver- sions, the logic inputs are protected against voltage spikes up to +15v, regardless of v dd . see the driver logic inputs (in_h, in_l) section. the max15018_/max15019_ are available with both high-side and low-side noninverting logic inputs or with noninverting high-side and inverting low-side logic inputs. see the functional diagrams and selector guide . the max15018a and max15019a are pin-for-pin replace- ments for the hip2100ib and hip2101ib, respectively. the max15018_/max15019_ are available in a space- saving, high-power, 8-pin so-ep package that can dissi- pate up to 1.95w at +70?. all devices operate over the -40? to +125? automotive temperature range. undervoltage lockout both the high- and low-side drivers feature separate uvlo protection that monitors each driver? input sup- ply voltage (bst and v dd ). the low-side driver uvlo threshold (v dd_uvlo ) is referenced to gnd and pulls both driver outputs low when v dd falls below 7.3v (typ). the high-side driver uvlo threshold (v bst_uvlo ) is ref- erenced to hs, and only pulls dh low when v bst falls below 6.9v (typ) with respect to hs. after the ic is first energized, and once v dd rises above its uvlo thresh- old, dl starts switching and either follows the in_l logic input (max15018a/max15019a) or is inverted with refer- ence to the in_l logic input (max15018b/ max15019b). at this time, the bootstrap capacitor is not charged, and dh does not switch since the bst-to-hs voltage is below v bst_uvlo . within a short time follow- ing engagement of low-side switching, c bst charges through v dd and causes v bst to exceed v bst_uvlo . dh then starts switching and follows in_h. for synchro- nous buck and half-bridge converter topologies, the bootstrap capacitor can charge up in one cycle. normal operation then begins in a few microseconds after the bst-to-hs voltage exceeds v bst_uvlo . in the two- switch forward topology, c bst takes more time (a few hundred microseconds) to charge and increase its volt- age above v bst_uvlo . the typical hysteresis for both uvlo thresholds is 0.5v. the bootstrap capacitor value should be selected carefully to avoid oscillations during turn-on and turn-off at the dh output. choose a capaci- tor value 20 times greater than the total gate capaci- tance of the mosfet. use a low esr-type x7r dielectric ceramic capacitor at bst (typically a 0.1? ceramic is adequate) and a parallel combination of 1? and 0.1? ceramic capacitors from v dd to gnd. the high-side mosfet? continuous on-time is limited due to the charge loss from the high-side driver? quiescent current. the maximum on-time is dependent on the size of c bst , i bst (190?, max), and v bst_uvlo .
output driver the max15018_/max15019_ drivers contain low on- resistance p-channel and n-channel devices in a totem pole configuration for the driver output stage. this allows for rapid turn-on and turn-off of high gate-charge (q g ) external switching mosfets. the drivers exhibit low drain-to-source resistance (r ds_on ), which decreases for higher values of v dd and for lower operating temperatures. lower r ds_on means higher source and sink currents from the ic, and results in faster switching speeds, since the exter- nal mosfet gate capacitance will charge and dis- charge at a quicker rate. the peak source and sink current provided by the drivers is typically 3a. propagation delay from the logic inputs to the driver outputs is matched to within 8ns (max) between the low-side and high-side drivers. turn-on and turn-off propagation delays are typically 35ns and 36ns. see figure 1. the internal drivers also contain break-before- make logic to eliminate shoot-through conditions that would cause unnecessarily high operating supply cur- rents, efficiency reduction, and voltage spikes at v dd . voltage at dl is approximately equal to v dd when in a high state, and zero when in a low state. voltage from dh to hs is approximately equal to v dd minus the diode drop of the integrated bootstrap diode when in a high state, and zero when in a low state. the high-side mosfet? continuous on-time is limited due to the charge loss from the high-side driver? quiescent cur- rent. the maximum on-time is dependent on the size of the bootstrap capacitor (c bst ), i bst (190? max), and v bst_uvlo . integrated bootstrap diode an integrated diode between v dd and bst is used in conjunction with an external bootstrap capacitor (c bst ) to provide the voltage required to turn on the high-side mosfet (see the typical operating circuit ). the inter- nal diode charges the bootstrap capacitor from v dd when the low-side switch is on, and isolates v dd when hs is pulled high when the high-side driver turns on. the internal bootstrap diode has a typical forward volt- age drop of 0.9v and has a 40ns (typ) turn-off/-on time. the turn-off time (reverse recovery time) depends on the reverse-recovery current and can be as low as 10ns. if a lower diode voltage-drop between v dd and bst is needed, connect an external schottky diode between v dd and bst. max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 9 figure 1. timing characteristics of logic inputs (max15018a/max15019a) in_l dl t d_off1 in_h v il v il dh 90% 10% 90% 10% v ih v ih t r t r t d_on1 t d_off1 t match = (t d_on2 - t d_on1 ) or (t d_off2 - t d_off1 ) t f t f t d_on2
max15018/max15019 bootstrap capacitor the bootstrap capacitor is used to ensure adequate charge is available to switch the high-side mosfet. this capacitor is charged from v dd through the internal bootstrap diode when the low-side mosfet is on. the bootstrap capacitor value should be selected carefully to avoid oscillations during turn-on and turn-off at the dh output. choose a capacitor value approximately 20 times greater than the total gate capacitance of the mosfet being switched. use a low-esr, x7r-type dielectric ceramic capacitor (typically a 0.1? ceramic is adequate). the high-side mosfet? continuous on- time is limited due to the charge loss from the high-side driver? quiescent current. the maximum on-time is dependent on the size of c bst , i bst (190? max), and v bst_uvlo. note that the bootstrap capacitor requires time to charge up to v dd , according to the time con- stant of the charging loop through the lower mosfet (see the typical operating circuit ). ensure that the lower mosfet is on for at least the minimum time required to charge c bst . driver logic inputs (in_h, in_l) the max15018_ are cmos (v dd /2) logic-input drivers, and the max15019_ are ttl-compatible logic-input dri- vers. the required logic-input levels are independent of v dd . for example, the ic can be powered by a 10v sup- ply while the logic inputs are provided from 12v cmos logic. additionally, the logic inputs are protected against voltage spikes up to 15v, regardless of v dd voltage. the ttl and cmos logic inputs have 400mv and 1.6v hys- teresis, respectively, to avoid double pulsing during sig- nal transition. the logic inputs are high-impedance pins (500k ? typ) and should not be left unconnected to ensure the input logic state is at a known level. with the logic inputs unconnected, the dh and dl outputs pull low as v dd rises up above the uvlo threshold. the pwm output from the controller must assume a proper state while powering up the device. applications information supply bypassing and grounding careful attention is required when choosing the bypass- ing and grounding scheme of the max15018_/ max15019_. peak supply and output currents may exceed 6a when both drivers are simultaneously driving large external capacitive loads in phase. supply drops and ground shifts create forms of negative feedback for inverterting topologies and may degrade the delay and transition times. ground shifts due to insufficient device grounding may also disturb other circuits sharing the same ac ground return path. any series inductance in the v dd , dh, dl, and/or gnd paths can cause oscilla- tions due to the very high di/dt when switching the max15018_/max15019_ with any capacitive load. place one or more 0.1? ceramic capacitors in parallel from v dd to gnd as close as possible to the device to bypass the input supply. use a ground plane to minimize ground return resistance and series inductance. place the external mosfets as close as possible to the max15018_/max15019_ to reduce trace length and fur- ther minimize board inductance and ac path resistance. power dissipation power dissipation in the max15018_/max15019_ is pri- marily due to power loss in the internal boost diode and the internal nmos and pmos fets. for capacitive loads, the total power dissipation for the device is: p d = (c l x v dd 2 x f sw ) + (i vddo + i bsto ) x v dd where c l is the combined capacitive load at dh and dl, v dd is the supply voltage, and f sw is the switching frequency of the ic. p d includes the power dissipated in the internal bootstrap diode (p diode ). the internal power dissipation reduces by p diode , if an external bootstrap schottky diode is used. the power dissipation in the internal boost diode (when driving a capacitive load) will be the charge through the diode per switching period multiplied by the maximum diode forward voltage drop (v f = 1v) as given in the following equation. p diode = c dh x (v dd - 1) x f sw x v f where c dh is the capacitive load at dh, v dd is the sup- ply voltage, f sw is the switching frequency of the con- verter, v f is the maximum diode forward voltage drop. the total power dissipation when using the internal boost diode will be p d and, when using an external schottky diode, will be p d - p diode . the total power dissipated in the device must be kept below the maxi- mum of 1.95w for the 8-pin so with exposed pad at t a = +70? ambient. 125v/3a, high-speed, half-bridge mosfet drivers 10 ______________________________________________________________________________________
layout information the max15018_/max15019_ drivers source and sink large currents to create very fast rise and fall edges at the gates of the switching mosfets. the high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. use the following pcb layout guidelines when designing with the max15018_/max15019_: it is important that the v dd voltage (with respect to ground) or bst voltage (with respect to hs) does not exceed 15v. voltage spikes higher than 15v from v dd to gnd or from bst to hs can damage the device. place one or more low-esl 0.1? decoupling ceramic capacitors from v dd to gnd and from bst to hs as close as possible to the part. the ceramic decoupling capacitors should be at least 20 times the gate capacitance being driven. there are two ac current loops formed between the ic and the gate of the mosfet being driven. the mosfet looks like a large capacitance from gate to source when the gate is being pulled low. the active current loop is from the mosfet driver output (dl or dh) to the mosfet gate, to the mosfet source, and to the return terminal of the mosfet driver (either gnd or hs). when the gate of the mosfet is being pulled high, the active current loop is from the mos- fet driver output, (dl or dh), to the mosfet gate, to the mosfet source, to the return terminal of the dri- vers decoupling capacitor, to the positive terminal of the decoupling capacitor, and to the supply connec- tion of the mosfet driver. the decoupling capacitor will be either c bst for the high-side mosfet or the v dd decoupling capacitor for the low-side mosfet. care must be taken to minimize the physical distance and the impedance of these ac current paths. solder the exposed pad of the 8-pin so-ep package to a large copper plane to achieve the rated power dissipation. max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers ______________________________________________________________________________________ 11 typical application circuits max15018a pwm1 pwm2 in_h in_l n v out n gnd v dd bst dh dl hs n n v dd = 8v to 12.6v v in = 0 to 125v figure 2. half-bridge converter application with secondary-side synchronous rectification
max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers 12 ______________________________________________________________________________________ typical application circuits (continued) max15018a max15019a pwm in_h in_l n v out n gnd v dd bst dh dl hs v dd = 8v to 12.6v v in = 0 to 125v figure 3. two-switch forward application
max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers ______________________________________________________________________________________ 13 functional diagrams max15018a bst dh hs v dd dl in_h in_l gnd v dd /2 cmos max15019a bst dh hs v dd dl in_h in_l gnd ttl max15018b bst dh hs v dd dl in_h in_l gnd v dd /2 cmos max15019b bst dh hs v dd dl in_h in_l gnd ttl so-ep so-ep so-ep so-ep selector guide part high-side driver low-side driver logic level pin compatible max15018aasa+ noninverting noninverting cmos (v dd /2) hip 2100ib MAX15018BASA+ noninverting inverting cmos (v dd /2) max15019aasa+ noninverting noninverting ttl hip 2101ib max15019basa+ noninverting inverting ttl chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 8 so s8e-14 21-0111
max15018/max15019 125v/3a, high-speed, half-bridge mosfet drivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 5/08 initial release 1 9/08 removed future product asterisk for the max15018b. 1

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